Semiconductor modules and methods of forming the same

ABSTRACT

Electronic modules, and methods of forming and operating modules, are described. The modules include a capacitor, a first switching device, and a second switching device. The electronic modules further include a substrate such as a DBC substrate, which includes an insulating layer between a first metal layer and a second metal layer, and may include multiple layers of DBC substrates stacked over one another. The first metal layer includes a first portion and a second portion isolated from one another by a trench formed through the first metal layer between the two portions. The first and second switching devices are over the first metal layer, a first terminal of the capacitor is electrically connected to the first portion of the first metal layer, and a second terminal of the capacitor is electrically connected to the second portion of the first metal layer, with the capacitor extending over the trench.

CROSS-REFERENCE TO RELATED APPLICATIONS

This is a divisional of U.S. application Ser. No. 13/690,103, filed onNov. 30, 2012, which claims priority to U.S. Provisional Application No.61/568,022, filed on Dec. 7, 2011. The disclosures of the priorapplications are considered part of and are incorporated by reference inthe disclosure of this application.

TECHNICAL FIELD

This invention relates to configurations for electronic modules formedof semiconductor electronic devices.

BACKGROUND

Power switching circuits such as bridge circuits are commonly used in avariety of applications. A circuit schematic of a prior art 3-phasebridge circuit 10 configured to drive a motor is shown in FIG. 1. Eachof the three half bridges 15, 25, and 35 in circuit 10 includes twotransistors (41-46), which are able to block voltage in a firstdirection and are capable of conducting current in the first directionor optionally in both directions. In applications where the transistorsemployed in the bridge circuit 10 are only capable of conducting currentin one direction, for example when silicon IGBTs are used, ananti-parallel diode (not shown) may be connected to each of thetransistors 41-46. The transistors 41-46 are each capable of blocking avoltage at least as large as the high voltage (HV) source 11 of thecircuit 10 when they are biased in the OFF state. That is, when thegate-source voltage V_(GS) of any of transistors 41-46 is less than thetransistor threshold voltage V_(th), no substantial current flowsthrough the transistor when the drain-source voltage V_(DS) (i.e., thevoltage at the drain relative to the source) is between 0V and HV. Whenbiased in the ON state (i.e. with V_(GS) greater than the transistorthreshold voltage), the transistors 41-46 are each capable of conductingsufficiently high current for the application in which they are used.The transistors 41-46 may be enhancement mode or E-mode transistors(normally off, V_(th)>0), or depletion mode or D-mode (normally on,V_(th)<0) transistors. In power circuits, enhancement mode devices aretypically used to prevent accidental turn on in which may cause damageto the devices or other circuit components. Nodes 17, 18, and 19 are allcoupled to one another via inductive loads, i.e., inductive componentssuch as motor coils (not shown in FIG. 1).

FIG. 2 a shows a prior art half bridge 15 of the full 3-phase motordrive in FIG. 1, along with the winding of the motor (inductivecomponent 21) between nodes 17 and 18 and the transistor 44, into whichthe motor current feeds. For this phase of power, transistor 44 iscontinuously on (V_(gs44)>V_(th)) and transistor 42 is continuously off(V_(gs42)<V_(th), i.e., V_(gs42)=0V if enhancement mode transistors areused), while transistor 41 is modulated with a pulse width modulation(PWM) signal to achieve the desired motor current. FIG. 2 b indicatesthe path of the current 27 during the time that transistor 41 is biasedon. For this bias, the motor current flows through transistors 41 and44, while no current flows through transistor 42 because transistor 42is biased off, and the voltage at node 17 is close to HV, so transistor42 blocks a voltage which is close to HV.

As used herein, the term “blocking a voltage” refers to a transistor,device, or component being in a state for which substantial current,such as current that is greater than 0.001 times the average operatingcurrent during regular on-state conduction, is prevented from flowingthrough the transistor, device, or component when a voltage is appliedacross the transistor, device, or component. In other words, while atransistor, device, or component is blocking a voltage that is appliedacross it, the total current passing through the transistor, device, orcomponent will not be greater than 0.001 times the average operatingcurrent during regular on-state conduction.

Referring to FIG. 2 c, when transistor 41 is switched off, no currentcan flow through transistor 41, and so the motor current flows in thereverse direction through transistor 42, which can occur whethertransistor 42 is biased on or off. Alternatively, an anti-parallelfreewheeling diode (not shown) can be connected across transistor 42, inwhich case the reverse current flows through the freewheeling diode.During such operation, the inductive component 21 forces the voltage atnode 17 to a sufficiently negative value to cause reverse conductionthrough transistor 42, and transistor 41 blocks a voltage which is closeto HV.

In many high voltage circuit applications, the circuit components aremounted on a substrate which includes a ceramic or other electricallyinsulating, high thermal conductivity material, such as AlN or Al₂O₃.The electrically insulating, high thermal conductivity material iscoated on at least one side (typically both sides) with a high heatcapacity metal, such as copper, thereby allowing for heat generated bythe circuit components to be dissipated. In particular, direct bondedcopper (DBC) substrates, which are formed by direct bonding of purecopper in a high temperature melting and diffusion process to a ceramicisolator such as AlN or Al₂O₃, are suitable substrates. An exemplary DBCprior art substrate, which includes copper layers 61 and 62 bonded toopposite sides of ceramic layer 60, is illustrated in FIG. 3. DBCsubstrates are currently only available as single layer substrates,unlike lower thermal conductivity printed circuit board (PCB)substrates, which can be formed with multiple insulating layers stackedon top of each other with a conductive metal layer between eachsuccessive insulating layer. The process used to form DBC substrates,which ensures sufficiently high thermal conductivity for high voltageapplications, can currently only be used to form DBC substrates thatinclude a single insulating/ceramic layer with pure copper layersdirectly bonded to each side. Hence, layouts that incorporate DBCsubstrates have been limited to single layers of metal-ceramic-metal DBCmaterial. While PCB substrates can be formed with multiple insulatinglayers each separated by a metal layer, which allows for moreflexibility in circuit layout, the thermal conductivity and/or heatcapacity of such substrates, which are lower than those of DBCsubstrates, are not sufficiently high for many high voltage circuits,for example bridge circuits used for power conversion

Referring back to FIGS. 2 a-2 c, the mode of switching illustrated inprior art FIGS. 2 a-2 c is commonly known as hard-switching. Ahard-switching circuit configuration is one in which the switchingtransistors are configured to have high currents passing through them assoon as they are switched ON, and to have high voltages across them assoon as they are switched OFF. More specifically, a hard-switchingcircuit configuration is one in which the switching transistors areconfigured to be switched from OFF to ON while the transistors aresustaining a large drain-source voltage, and to have high currentspassing through them as soon as they are turned ON. Transistors switchedunder these conditions are said to be “hard-switched”. Hard-switchedcircuits tend to be relatively simple and to be operable at a wide rangeof output load powers. However, hard-switched circuits are typicallyprone to large voltage overshoots and hence high levels of EMI.Alternative circuit configurations make use of additional passive and/oractive components, or alternatively signal timing techniques, to allowthe transistors to be “soft-switched”. A soft-switching circuitconfiguration is one in which the switching transistors are configuredto be switched ON during zero-current (or near zero-current) conditionsor during zero-voltage (or near zero-voltage) conditions. Soft-switchingmethods and configurations have been developed to reduce switchinglosses and to address the high levels of electro-magnetic interference(EMI) and associated ringing observed in hard-switched circuits,especially in high current and/or high voltage applications. Whilesoft-switching can in many cases alleviate these problems, the circuitryrequired for soft switching typically includes many additionalcomponents, resulting in increased overall cost and complexity.Soft-switching also typically requires that the circuits be configuredto switch only at specific times when the zero-current or zero-voltageconditions are met, hence limiting the control signals that can beapplied and in many cases reducing circuit performance. Furthermore, dueto the required resonance conditions for soft-switching operation, theoutput load for each soft-switched circuit must be within a given rangeof values, thereby limiting the operation range of the circuit. Hence,alternative configurations and methods are desirable for hard-switchedpower switching circuits in order to prevent excessively high voltageovershoots and to maintain sufficiently low levels of EMI while allowingfor a wide range of output loads.

SUMMARY

In a first aspect of the invention, an electronic module is described.The electronic module includes a capacitor, a first switching device(105/105′) comprising a first transistor (41/109), and a secondswitching device (106/106′) comprising a second transistor (42/108). Theelectronic module further includes a substrate (74) comprising aninsulating layer (60) between a first metal layer (61/75) and a secondmetal layer (62), the first metal layer including a first portion (37)and a second portion (38), the second portion being electricallyisolated from the first portion by a trench (76) formed through thefirst metal layer between the first portion and the second portion. Thefirst and second switching devices are over the first metal layer, afirst terminal of the capacitor is electrically connected to the firstportion of the first metal layer, and a second terminal of the capacitoris electrically connected to the second portion of the first metallayer, with the capacitor extending over the trench.

In a second aspect of the invention, an electronic module is described.The electronic module includes a first substrate (74) comprising a firstmetal layer (61/75) on a first insulating layer (60), the first metallayer including a first portion (206) and a second portion (208), and asecond substrate (96/96′) comprising a second insulating layer (60/97)between a second metal layer (99/62) and a third metal layer (98/61),the second substrate having a second surface (262) and a third surface(261) on an opposite side of the second substrate from the secondsurface, the second insulating layer having a smaller area than thefirst insulating layer. The electronic module further includes a firstsemiconductor device (105/105′). The second substrate is mounted overthe first portion of the first metal layer without being over the secondportion of the first metal layer, with the second surface of the secondsubstrate directly contacting the first metal layer, and the firstsemiconductor device is mounted on the third surface of the secondsubstrate.

In a third aspect of the invention, an electronic module is described.The electronic module includes a first substrate (74) comprising a firstinsulating layer (60) between a first metal layer (62) and a secondmetal layer (61/75), and a second substrate (96/96′) comprising a secondinsulating layer (60/97) between a third metal layer (99/62) and afourth metal layer (98/61). The second substrate has a smaller area thanthe first substrate, and the second substrate is mounted on a firstportion (206) of the first substrate with the third metal adjacent to orcontacting the second metal. The electronic module further includes afirst switching device (106/106′) having a first gate and a firstsource, and a second switching device (105/105′) having a second gateand a second source. The first switching device is mounted on the secondmetal layer of the first substrate and the second substrate is betweenthe second switching device and the first substrate.

Electronic modules described herein can includes one or more of thefollowing features. A drain of the first transistor (41/109) can beelectrically connected to a source of the second transistor (42/108),and the first and second transistors can both be over the first portionof the first metal layer. The first portion of the first metal layer caninclude means to electrically connect the first portion of the firstmetal layer to a DC ground or to a first DC voltage, and the secondportion of the first metal layer can include means to electricallyconnect the second portion of the first metal layer to a second DCvoltage. The capacitor can be configured to stabilize a voltagedifference between the first and the second portions of the first metallayer. The first or second transistor can be a III-Nitride transistor.The substrate can include a direct bonded copper substrate. Theelectronic module can further include a second substrate comprising asecond insulating layer between a third metal layer and a fourth metallayer, the second substrate being over a third portion of the firstmetal layer but not being over the first and second portions of thefirst metal layer, wherein the second substrate is between the secondtransistor and the first substrate, and the first transistor is over thefirst or second portion of the first metal layer.

The first substrate and the second substrate can include direct bondedcopper substrates. The electronic module can further include a secondsemiconductor device (104/106) mounted on the second portion of thefirst metal layer. The first semiconductor device (103/105) can comprisea first transistor (41/109), the second semiconductor device (104/106)can comprise a second transistor (42/108), and a source of the firsttransistor and a drain of the second transistor can be electricallyconnected to the third metal layer. The first transistor or the secondtransistor can be a III-Nitride transistor. The first metal layer canfurther include a third portion (38), wherein the third portion iselectrically isolated from the second portion (208) by a trench formedthrough the first metal layer between the third portion and the secondportion. The electronic module can further comprise a capacitor, whereina first terminal of the capacitor is electrically connected to the thirdportion of the first metal layer, a second terminal of the capacitor iselectrically connected to the second portion of the first metal layer,and the capacitor extends over the trench. A drain of the firsttransistor (41) can be electrically connected to the third portion (38)of the first metal layer. The first semiconductor device can furthercomprise a third transistor (108), a source of the third transistor canbe electrically connected to a drain of the first transistor (109), anda drain of the first transistor can be electrically connected to thethird portion (38) of the first metal layer.

The electronic module can further comprise a third substrate (126)comprising a third insulating layer (60) between a fourth metal layer(62) and a fifth metal layer (61), the third insulating layer having asmaller area than the second insulating layer, with the third substratemounted directly over the third surface of the second substrate. Thefirst semiconductor device can include a first transistor, the secondsemiconductor device can include a second transistor, and a source ofthe first transistor and a drain of the second transistor can both beelectrically connected to the third metal layer. The first metal layercan further include a third portion, with the third portion beingelectrically isolated from the second portion by a trench formed throughthe first metal layer between the third portion and the second portion.The electronic module can further comprise a capacitor, with a firstterminal of the capacitor electrically connected to the third portion ofthe first metal layer, a second terminal of the capacitor electricallyconnected to the second portion of the first metal layer, and thecapacitor extending over the trench. A drain of the first transistor canbe electrically connected to the third portion of the first metal layer.The first semiconductor device can further comprise a third transistor,with a source of the third transistor electrically connected to a drainof the first transistor, and a drain of the first transistorelectrically connected to the third portion of the first metal layer.

The first and second semiconductor devices can comprise transistors, thetransistors being part of a half bridge. The first source can beelectrically connected to a first source lead, the first gate can beelectrically connected to a first gate lead, the second source can beelectrically connected to a second source lead, and the second gate canbe electrically connected to a second gate lead. The first source leadand first gate lead can be mounted on the second metal layer of thefirst substrate, and the second source lead and second gate leads can bemounted on the fourth metal layer of the second substrate. The firstsource lead can extend away from a surface of the first substrate, thesecond gate lead can extend away from a surface of the second substrate,the first source lead can include a bend in a direction away from thesecond switching device, and the second gate lead can include a bend ina direction away from the first switching device.

In a fourth aspect of the invention, a method of manufacturing anelectronic module is described. The method includes providing a firstsubstrate comprising a first metal layer on a first insulating layer,the first substrate having a first surface, with the first substrateincluding a first portion and a second portion. The method furtherincludes providing a second substrate comprising a second insulatinglayer between a second metal layer and a third metal layer, the secondsubstrate having a second surface and a third surface on an oppositeside of the second substrate from the second surface. The method alsoincludes mounting the second substrate over the first surface in thefirst portion of the first substrate with the second surface between thethird surface and the first surface; and mounting a first semiconductordevice on the third surface of the second substrate.

Methods of manufacturing electronic modules described herein can includeone or more of the following features. The method can further comprisemounting a second semiconductor device on the first surface of the firstsubstrate in the second portion of the first substrate. The firstsemiconductor device or the second semiconductor device can be atransistor. The transistor can comprise source, gate, and drainelectrodes, each of the electrodes being on a first side of thetransistor. The transistor can be a III-Nitride transistor. The firstsemiconductor device or the second semiconductor device can be aswitching transistor which is configured to be hard-switched. Aswitching time of the switching transistor can be about 3 nanoseconds orless. Mounting the first semiconductor device on the second substrate ormounting the second semiconductor device on the first substrate can beperformed prior to mounting the second substrate over the first surfacein the first portion of the first substrate. The second surface of thesecond substrate can be attached directly to the first surface of thefirst substrate in the first portion of the first substrate. The firstsurface of the first substrate can comprise a surface of the first metallayer, the second surface of the second substrate can comprise a surfaceof the second metal layer, and the third surface of the second substratecan comprise a surface of the third metal layer.

The method can further comprise partially removing the first metallayer. Partially removing the first metal layer can comprise forming anisolation trench through the first metal layer. Partially removing ofthe first metal layer can be performed prior to mounting the secondsubstrate over the first surface in the first portion of the firstsubstrate. Mounting the second substrate over the first portion of thefirst substrate can comprise soldering the second surface of the secondsubstrate to the first portion of the first surface of the firstsubstrate. The first insulator layer or the second insulator layer cancomprise a ceramic material. One or more of the first, second, or thirdmetal layers can comprise copper. The first substrate or the secondsubstrate can be a direct bonded copper (DBC) substrate.

An area of the first surface of the first substrate can be larger thanan area of the second surface of the second substrate. The electronicmodule can comprise a half bridge. The electronic module can comprise apower inverter or a power converter. The method can further comprisemounting a capacitor having a first terminal and a second terminal onthe electronic module. The method can further comprise forming a trenchthrough the first metal layer in the second portion of the firstsubstrate. Mounting the capacitor on the electronic module can compriseconnecting the first terminal to the first metal layer on a first sideof the trench and connecting the second terminal to the first metallayer on a second side of the trench. The first substrate can furthercomprise a fourth metal layer on an opposite side of the firstinsulating layer from the first metal layer.

In a fifths aspect of the invention, an electronic device is described.The electronic device includes an enhancement-mode transistor comprisinga first source electrode, a first gate electrode, a first drainelectrode, and a first semiconductor layer. The first source and firstgate electrodes are on an opposite side of the first semiconductor layerfrom the first gate electrode. The electronic device further includes adepletion-mode transistor comprising a second source electrode and asecond gate electrode, the second source electrode being over a secondsemiconductor layer. The enhancement-mode transistor is mounted directlyon top of or over the second source electrode, with the first drainelectrode in direct electrical contact with the second source electrode.

Electronic devices and components described herein can include one ormore of the following features. The depletion-mode transistor canfurther comprise a second drain electrode, and the second source anddrain electrodes can both be on a first side of the second semiconductorlayer. The depletion-mode transistor can be a lateral device. Theenhancement-mode transistor can be a silicon-based transistor. Thedepletion-mode transistor can be a III-Nitride transistor. The firstsource electrode can be electrically connected to the second gateelectrode. The depletion-mode transistor can comprise an insulator layeron the semiconductor layer, with the second source electrode on theinsulator layer. The depletion-mode transistor can comprise a deviceactive area and a non-active area, wherein a device channel is in thesemiconductor layer in the device active area but not in thesemiconductor layer in the non-active area, and the insulator layer isover both the device active area and the non-active area. Theenhancement-mode transistor can be on the insulating layer and bedirectly over a portion of the device active area and a portion of thenon-active area. The depletion-mode transistor can have a higherbreakdown voltage than the enhancement-mode transistor.

In a sixth aspect of the invention, a method of forming an electronicdevice is described. The method includes providing an enhancement-modetransistor comprising a first source electrode, a first gate electrode,a first drain electrode, and a first semiconductor layer, wherein thefirst source and first gate electrodes are on an opposite side of thefirst semiconductor layer from the first gate electrode. The method alsoincludes providing a depletion-mode transistor comprising a secondsource electrode and a second gate electrode, the second sourceelectrode being over a second semiconductor layer. The method furtherincludes mounting the enhancement-mode transistor directly on top of orover the second source electrode, with the first drain electrode indirect electrical contact with the second source electrode.

Methods of forming electronic devices and modules described herein caninclude one or more of the following features. The depletion-modetransistor can be a lateral device. The method can further comprise wirebonding the second gate electrode to the first source electrode.

In a seventh aspect of the invention, a method of operating a powerinverter is described. The method includes connecting the power inverterto a high voltage supply, the high voltage supply providing a voltage ofat least 500V, and switching the switching device from an on state to anoff state or from an off state to an on state. In the on state theswitching device conducts between 40 and 50 Amps, in the off state theswitching device blocks the voltage provided by high voltage supply, aswitching time of the switching is less than 10 nanoseconds, and thevoltage across the switching device never exceeds 1.35 times the voltageprovided by the high voltage supply.

Methods of operating a power inverter described herein can include oneor more of the following features. The switching time can be less than 5nanoseconds. The voltage across the switching device never exceeds 700V.

The details of one or more embodiments of the subject matter describedin this specification are set forth in the accompanying drawings and thedescription below. Other features, aspects, and advantages of thesubject matter will become apparent from the description, the drawings,and the claims.

DESCRIPTION OF DRAWINGS

FIG. 1 illustrates a prior art circuit schematic of a 3-phase bridgecircuit.

FIGS. 2 a-c illustrate portions of the prior art 3-phase bridge circuitof FIG. 1 under various operating conditions.

FIG. 3 is a perspective view of a prior art direct bonded copper (DBC)substrate.

FIGS. 4 a-b illustrate circuit schematics of a portion of a bridgecircuit.

FIGS. 5-7 are plan view schematic diagrams of electronic modulesfeaturing bridge circuits.

FIGS. 8A and 8B are cross-sectional views along portions of theelectronic module of FIG. 7.

FIGS. 9A-E illustrate a process of forming the electronic module of FIG.7.

FIGS. 10A-B illustrate electronic devices that can be used in electronicmodules.

FIGS. 11A-F illustrate a process for manufacturing an electronic devicethat can be used in electronic modules.

FIG. 12 is a plan view schematic diagram of an electronic modulefeaturing a half bridge.

FIGS. 13A-B are plots of current and voltage characteristics of a powerinverter during operation.

Like reference symbols in the various drawings indicate like elements.

DETAILED DESCRIPTION

Described herein are electronic components and methods suitable formaintaining low levels of EMI in electronic power switching circuits,thereby allowing for higher circuit stability and improved performance.The electronic components can also have a reduced size as compared toconventional components, thereby allowing for lower production costs.

The transistors or other switching devices in the circuits describedherein are typically configured to be hard-switched, as previouslydescribed, at very high switching rates (i.e., with very small switchingtimes). When a transistor of one of the circuits herein is in the offstate with no substantial current flowing through it, it typicallyblocks a voltage between its drain and source terminals which is closeto the circuit high voltage. When a transistor of one of the circuitsherein is in the on state, it typically has substantial drain-sourcecurrent passing through with only a small voltage across the device. Theswitching time of a switching transistor switched under hard-switchingconditions is defined as follows. When the transistor is switched fromthe off state described above to the on state described above, thecurrent through the device begins to increase at the onset of switching,the rate of increase being adjustable by adjusting the conditions of thecontrol circuitry, while the voltage across the device remainsapproximately the same. The drain-source voltage across the device doesnot drop substantially until the point at which substantially all theload current is passing through the transistor. The time that elapsesbetween the onset of switching and the drop in voltage across the deviceis referred to as the “switching time” for turning the transistor on.More specifically, the “switching time” for turning the transistor oncan be defined as the time that elapses between the point at which thedrain-source voltage equals 90% of the blocking voltage and the point atwhich the drain-source voltage equals 10% of the blocking voltage. Thetotal voltage switched across the device divided by the switching time(dV/dt) is referred to as the “voltage switching rate” or just the“switching rate”.

In the case of switching the transistor from the on state to the offstate, the voltage across the device increases to the off state voltageapproximately at the onset of switching, while the decrease in currentfrom the on state value to the off state value takes a longer time, therate of decrease again being adjustable by adjusting the conditions ofthe control circuitry. The time that elapses between the onset ofswitching and the drop to zero current through the device is referred toas the “switching time” for turning the transistor off. Morespecifically, the “switching time” for turning the transistor off can bedefined as the time that elapses between the point at which thedrain-source voltage equals 10% of the blocking voltage and the point atwhich the drain-source voltage equals 90% of the blocking voltage. Thetotal current switched through the device divided by the switching time(dI/dt) is referred to as the “current switching rate” or just the“switching rate”. In general, while shorter switching times (andtherefore higher switching rates) typically result in lower switchinglosses, they typically also cause higher levels of EMI, which candegrade circuit components or damage them such that they are renderedinoperable.

In order to ensure proper operation of circuits having a schematiccircuit layout such as in FIGS. 1-2, the DC High Voltage node 11 must bemaintained as an AC ground. That is, node 11 is preferably capacitivelycoupled to DC ground 12 by connecting one terminal of a capacitor 51 tothe High Voltage node 11 and the other terminal of the capacitor toground 12, as illustrated in FIG. 4 a. Hence, when either of transistors41 or 42 is switched on or off, the capacitor 51 can charge or dischargeas needed to provide the current necessary to maintain a substantiallyconstant voltage at the high- and low-voltage sides of the circuit. TheEMI produced by higher switching rates typically results in thecapacitor 51 needing to provide higher current levels over shorterperiods of time in order to stabilize the circuit. In many cases, theconductive connectors between the capacitor 51 and the circuit havelarge parasitic inductance, represented by inductors 52 and 53 in FIG. 4b. This parasitic inductance prevents current passing through capacitor51 from being able to switch sufficiently quickly, thereby preventingcapacitor 51 from providing current at a fast enough rate to preventvoltage variations across transistors 41 or 42 after either of thetransistors is switched on or off. This can result in deleteriouseffects such as voltage oscillations (i.e., ringing) and excessivelylarge EMI. In particular, excessively large voltage oscillations acrossany of the transistors in the circuit can result in the transistorbreaking down and being rendered inoperable.

FIGS. 5-7 are schematic layouts of electronic components, i.e., bridgecircuits. The circuit schematic of each of the electronic components ofFIGS. 5-7 is similar to that shown in FIG. 1, except that the electroniccomponents of FIG. 5-7 also each include a capacitor 71/91 between thehigh voltage and ground planes. The electronic components of FIGS. 5-7include features designed to substantially reduce parasitic inductancesin the circuit, thereby resulting in circuits that can operate at higherswitching speed with lower losses.

Referring to the schematic layout of a bridge circuit illustrated inFIG. 5, the components of the bridge circuit are all mounted on a singlecommon DBC substrate 74 having a metal layer 75 bonded to an insulatingor ceramic material. Half bridge 121 includes transistors 81 and 82,half bridge 122 includes transistors 83 and 84, and half bridge 123includes transistors 85 and 86. Transistors 81-86 are verticaltransistors, each having a source and gate electrode on an opposite sideof the transistor from the drain electrode, and are mounted on thesubstrate with the drains contacting the metal layer 75. Alternatively,lateral transistors, for which the source, gate, and drain are each onthe same side of the device, could be used for transistors 81-86, inwhich case the drain may be connected to the metal layer 75, for exampleby wire bonding. Examples of lateral transistors that could be usedinclude III-Nitride transistors such as III-Nitride high electronmobility transistors (HEMTs). As used herein, the terms III-Nitride orIII-N materials, layers, devices, structures, etc., refer to a material,layer, device, or structure comprised of a compound semiconductormaterial according to the stoichiometric formula Al_(x)In_(y)Ga_(z)N,where x+y+z is about 1. In a III-Nitride or III-N device, such as atransistor or HEMT, the conductive channel can be partially or entirelycontained within a III-N material layer.

A trench 76 is formed through the metal layer, exposing the ceramicmaterial in the trench region and electrically isolating metal layer 75around each of transistors 82, 84, and 86 from the remainder of metallayer 75. Leads 77, which are electrically connected to metal layer 75in the lower portion 37 (i.e., the portion below the trench 76) of thesubstrate, are configured to be connected to a DC ground, therebymaintaining the metal layer 75 in the lower portion 37 at DC ground.Leads 78, which are electrically connected metal layer 75 in the upperportion 38 (i.e., the portion above the trench 76) of the substrate, areconfigured to be connected to a DC high voltage supply (not shown),thereby maintaining the metal layer 75 in the upper portion 38 at a DChigh voltage. As used herein, two or more contacts or other items suchas conductive layers or components are said to be “electricallyconnected” if they are connected by a material which is sufficientlyconducting to ensure that the electric potential at each of the contactsor other items is substantially the same or about the same regardless ofbias conditions. Gate leads 87 and source leads 88 are electricallyconnected to the respective gates and sources of transistors 81-86, forexample with wire bonds 39 as shown (for clarity, only one wire bond isnumbered 39 in FIG. 5). The gate leads 87 and source leads 88 are eachelectrically isolated from the drains of their respective transistors bytrenches 56 formed through the entire thickness of metal layer 75 andsurrounding each of the gate leads 87 and source leads 88. Output leads79, which are configured to be connected to an inductive load (notshown), are each electrically connected to metal layer 75 in the regionssurrounding transistors 82, 84, and 86, respectively.

As seen in FIG. 5, a relatively large spatial separation exists betweenportions 37 and 38, and so capacitor 71, which capacitively couples theground plane in portion 37 to the high voltage plane in portion 38, isexternally mounted, with conductive connectors 72 and 73 connecting thecapacitor to metal layer 75 in portions 37 and 38, respectively. Becauseconnectors 72 and 73 are relatively long to accommodate for the largespatial separation between portions 37 and 38, they tend to have largeparasitic inductance, corresponding to large values of inductors 52 and53 in FIG. 4 b. As such, while the electronic component of FIG. 5 may beoperable when the transistors are switched at lower switching ratesand/or at low enough switching current and voltage levels withsufficiently high switching times, at higher switching rates and/orhigher switching voltages or currents, the parasitic inductances in thecircuit may lead to intolerably high levels of EMI and voltagefluctuations/oscillations. Specifically, if the rate of change ofvoltage (dV/dt) or the rate of change of current (dI/dt) through oracross the transistors during transistor switching is too high, voltagefluctuations/oscillations and EMI can reduce the efficiency andperformance of the circuit or cause one or more of the circuitcomponents to fail.

FIG. 6 shows another schematic layout of an electronic component, i.e.,a bridge circuit. The electronic component of FIG. 6 is similar to thatof FIG. 5, except that the layout has been modified to include couplingcapacitors 91 between the high voltage and ground planes that aredirectly over the single DBC substrate 74, thereby eliminating the needfor long connectors on either side of the coupling capacitors andreducing the parasitic inductance in the circuit. Specifically, theshape of the trench 76 formed through metal layer 75 of the DBCsubstrate has been modified so that portion 38 includes regions 92between transistors 82 and 84 and between transistors 84 and 86. Themetal layer 75 in regions 92 extends down towards the metal layer 75 inportion 37, and is separated from the metal layer 75 in portion 37 bythe width of the trench 76, which can be less than 2 cm, for exampleabout 1 cm or less. Capacitors 91 are mounted directly over the trench76, as shown, with a first terminal of the capacitor 91 being connectedto metal layer 75 on one side of the trench and a second terminal of thecapacitor 91 being connected to metal layer 75 on the opposite side ofthe trench. The points on metal layer 75 to which each of the twoterminals of the capacitor are connected can be less than 2 cm from thetrench and/or less than 4 cm from one another, thereby allowing for acompact design with low parasitic inductance.

While the layout of FIG. 6 can substantially reduce parasiticinductances in the circuit as compared to the layout of FIG. 5, anycurrent flowing through capacitors 91 and any of transistors 81, 83, or85 must flow through a relatively narrow region 92, which can stillresult in parasitic inductances in the circuit that may be too high forsome applications, for example applications in which the rate at whichvoltage and/or current switching across or through any of thetransistors is very high. While increasing the widths of regions 92 canresult in lower parasitic inductance, the overall size and cost of theelectronic component also increases. However, compact layouts for whichcurrent flowing between the coupling capacitors and transistors isspread over a large width of conducting material are desirable in orderto improve circuit speed and performance while at the same timeminimizing the footprint and material costs.

FIG. 7 shows a compact layout for a bridge circuit that further resultsin reduced parasitic inductances, as compared to the layouts of FIGS. 5and 6. The compact design is achieved by using additional DBC substrates94-96 stacked over DBC substrate 74, such that current passing throughany of capacitors 91 is able to pass underneath the high-side devices101, 103, or 105, and is therefore not confined to a relatively narrowchannel, as further described below.

The bridge circuit illustrated in FIG. 7 is formed on a DBC substrate 74and includes transistors 101-106, which are lateral transistors, havinga source, gate, and drain all on the same side or on a commonsemiconductor layer of the device. The lateral transistors 101-106 areformed with each of the source, gate, and drain being on one or more ofthe device semiconductor layers, with the device semiconductor layer orlayers being between DBC substrate 74 and each of the source, gate, anddrain. The electronic component of FIG. 7 further includes additionalDBC substrates 94-96 stacked over DBC substrate 74, with high-sidetransistors 101, 103, and 105 of half bridges 121″-123″, respectively,being over the substrates 94, 95, and 96. As seen in FIG. 8A, which is across-sectional view along dashed line 100 of the electronic componentof FIG. 7, DBC substrate 95, which includes metal layers 98 and 99 onopposite sides of insulating/ceramic layer 97, is secured over a sectionof the lower portion 37 (i.e., the portion in which metal layer 75 isconnected to ground, labeled in FIG. 7) of DBC substrate 74. Metal layer99 of DBC substrate 95 can be electrically connected to metal layer 75of DBC substrate 74, and for example can be secured to metal layer 75with a conductive adhesive or epoxy. Lateral power transistor 103 isformed over metal layer 98, with its source electrode wire bonded toboth a source lead 88 (shown in FIG. 7 but not in FIG. 8A) and to metallayer 98 of DBC substrate 95, its gate electrode wire bonded to gatelead 87 (shown in FIG. 7 but not in FIG. 8A), and its drain electrodewire bonded to metal layer 75 in portion 38 of DBC layer 74.

Referring back to FIG. 7, output leads 79 are each electricallyconnected to the upper metal layer (layer 98 in FIG. 8A) of DBCsubstrates 94-96. Low-side transistors 102, 104, and 106, which aremounted over portion 37 of DBC substrate in sections that do not includeadditional DBC substrates, are each configured as follows. The sourceelectrode is wire bonded to metal layer 75 in portion 37 and to a sourcelead 88, the gate electrode is wire bonded to a gate lead 87, and thedrain electrode is wire bonded to the upper metal layer (i.e., the metallayer furthest from DBC substrate 74) of DBC substrates 94-96, as shown.

In the electronic component of FIG. 7, current which flows from any ofcapacitors 91 to the source of any of transistors 102, 104, or 106, orin the opposite direction, flows through metal layer 75 and cantherefore pass underneath at least one of transistors 101, 103, or 105,since metal layer 75 extends underneath transistors 101, 103, and 105.As such, current is not confined laterally to a relatively narrowchannel, as was the case in FIG. 6. Consequently, parasitic inductancesin this electronic component are reduced as compared to those in theelectronic component of FIG. 6. Furthermore, since narrow regions 92included in the electronic component of FIG. 6 are not needed in theelectronic component of FIG. 7, the electronic component of FIG. 7 canbe made more compact and can have a smaller footprint than that of FIG.6.

FIG. 8B, which is a cross-sectional view along dashed line 90 of theelectronic component of FIG. 7, illustrates the configuration of sourceand gate leads 88 and 87, respectively, of transistors 103 and 104.Because of the compact design of the electronic component of FIG. 7, andspecifically due to the small spacing between transistors 103 and 104,the leads 87 and 88 are bent to prevent accidental shorting of thedevices to one another. That is, the leads 87 and 88 of transistor 103include a bend in a direction away from transistor 104, and the leads 87and 88 of transistor 104 include a bend in a direction away fromtransistor 103, in order to increase the minimum spacing 57 between theleads of adjacent devices.

An example method of forming the electronic component of FIG. 7 isillustrated in FIGS. 9A-9E. Referring to FIG. 9A, a first DBC substrate74, along with DBC substrates 94-96, are provided. DBC substrates 94-96each have a cross-sectional area which is smaller than that of DBCsubstrate 74. Referring to FIG. 9E, in particular, since each of DBCsubstrates 94-96 must fit within the area of DBC substrate 74 withoutoverlapping one another, DBC substrates 94-96 each have across-sectional area which is less than ⅓ that of DBC substrate 74.Furthermore, since sufficient room needs to be maintained for portion 38as well as for transistors 102, 104, and 106, DBC substrates 94-96 caneach have a cross-sectional area which is less than ⅙ that of DBCsubstrate 74.

Referring to FIG. 9B, trench 76 is then formed through metal layer 75 ofDBC substrate 74, and trenches 56 are formed in the upper metal layersof each of DBC substrates 75 and 94-96. Next, as shown in FIG. 9C,transistors 101, 103, and 105 are each secured to the upper metalsurfaces of DBC substrates 94, 95, and 96, respectively, and transistors102, 104, and 106 are secured to metal layer 75 in portion 37 (i.e., theportion of DBC substrate 74 that is on the same side of trench 76 asleads 77) of DBC substrate 74. Capacitors 91 are secured over trench 76with one terminal contacting metal layer 75 in portion 37 and theopposite terminal contacting metal layer 75 in portion 38 (i.e., theportion of DBC substrate 74 that is on the same side of trench 76 asleads 78). Ground leads 77 are secured and electrically connected tometal layer 75 in portion 37, high voltage leads 78 are secured andelectrically connected to metal layer 75 in portion 38, and output leads79 are secured to and electrically connected to the upper metal surfacesof each of DBC substrates 94-96. Source leads 88 and gate leads 87 areattached proximal to each of transistors 101-106, as shown.

Next, as illustrated in FIG. 9D, DBC substrates 94-96 are secured overDBC substrate 74, with metal layer 75 of DBC substrate 74 contactingeach of the bottom metal layers of DBC substrates 94-96. Finally, wirebonds 39 are formed, resulting in the electronic component shown in FIG.9E, which is the same as that of FIG. 7 (for the sake of clarity, onlyone wire bond 39 is labeled in FIGS. 7 and 9E).

Transistors 101-106 could be enhancement-mode (E-mode) transistors,having a positive threshold voltage, or depletion-mode (D-mode)transistors, having a negative threshold voltage. In many high voltageor power switching applications, it is preferable that the transistorsbe enhancement-mode devices in order to prevent damage to the circuit incase of failure of any of transistors 101-106. Transistors 101-106 canalso include an insulating or semi-insulating layer, for example asemi-insulating substrate such as Al₂O₃, silicon, or silicon carbide,between some or all of the device semiconductor layers and the DBCsubstrate on which they are mounted, in order to electrically isolateportions of the device from the DBC substrate.

While in FIG. 7 transistors 101-106 are each shown to be single lateraltransistors, other devices could be used instead. For example, aswitching device such as hybrid device 107, shown in FIGS. 10A and 10B,could be used in place of any or each of switching transistors 101-106.Since switching devices consisting of high-voltage enhancement-modetransistors can be difficult to fabricate reliably, one alternative to asingle high-voltage E-mode transistor is to combine a high-voltageD-mode transistor 108 with a low-voltage E-mode transistor 109 in theconfiguration of FIGS. 10A and 10B to form a hybrid device 107. Hybriddevice 107 can be operated in the same way as a single high-voltageE-mode transistor, and in many cases achieves the same or similar outputcharacteristics as a single high-voltage E-mode transistor. FIG. 10Ashows a plan view schematic diagram of hybrid device 107, and FIG. 10Bshows a circuit schematic of hybrid device 107. Hybrid device 107includes a high-voltage D-mode transistor 108 and a low-voltage E-modetransistor 109. In the configuration illustrated in FIGS. 10A and 10B,E-mode transistor 109 is a vertical transistor, having its drainelectrode 113 on the opposite side of the device's semiconductor layersfrom its source electrode 111 and gate electrode 112, and D-modetransistor 108 is a lateral transistor, having its source electrode 114,gate electrode 115, and drain electrode 116 all on the same side of thedevice's semiconductor layers. However, other configurations for each oftransistors 108 and 109 are possible as well. In some implementations,the D-mode transistor 108 is a III-Nitride transistor. In someimplementations, the E-mode transistor 109 is a silicon-basedtransistor, while in other implementations it is a III-Nitridetransistor.

The source electrode 111 of the low-voltage E-mode transistor 109 andthe gate electrode 115 of the high-voltage D-mode transistor 108 areboth electrically connected together, for example with wire bonds 39(shown in FIG. 10A), and together form the source 121 (shown in FIG.10B) of the hybrid device 107. The gate electrode 112 of the low-voltageE-mode transistor 109 forms the gate 122 (shown in FIG. 10B) of thehybrid device 107. The drain electrode 116 of the high-voltage D-modetransistor 108 forms the drain 123 (shown in FIG. 10B) of the hybriddevice 107. The source electrode 114 of the high-voltage D-modetransistor 108 is electrically connected to the drain electrode 113 ofthe low-voltage E-mode transistor 109. As seen in FIG. 10A, drainelectrode 113, which is on the opposite side of the E-mode transistor109 from the source and drain electrodes 111 and 112, respectively, canbe electrically connected to source electrode 114 by mounting thelow-voltage E-mode transistor 109 directly on top of or over the sourceelectrode 114 with the drain electrode 113 (which is on the bottom ofE-mode transistor 109 and is shown in FIG. 10B) directly contacting thesource electrode 114, for example by using a conductive solder or resin.As such, the footprint (and therefore the cross-sectional area) of thelow-voltage E-mode transistor 109 can be smaller than that of thehigh-voltage D-mode transistor 108, and in particular the footprint ofthe low-voltage E-mode transistor 109 can be smaller than that of thesource electrode 114 high-voltage D-mode transistor 108.

A method for forming a hybrid device 107 such as that shown in FIG. 10Ais illustrated in FIGS. 11A-11F. First, the high-voltage D-modetransistor 108 is formed, as shown in FIGS. 11A-11E. Referring to FIG.11A, a III-Nitride material structure which includes III-Nitride layers131 and 132 is formed on a substrate 130. A two-dimensional electrodegas (2 DEG) channel 133 is induced in the III-Nitride material structureas a result of a compositional difference between layers 131 and 132.Next, a device active area 140 and a non-active area 141 are defined asfollows. The non-active area 141 is treated such that the 2 DEG channel133 is removed from the non-active area 141 but remains in the activearea. Such a treatment can include implanting regions 134 with ions, asshown in FIG. 11A. Alternatively, the treatment can include etching awaysome or all of the III-Nitride material layers 131 and/or 132 in thenon-active area 141. For example, the etch can be performed to a depththat is greater than the depth of the 2 DEG channel 133, such that thematerial which contained the 2 DEG channel 133 is removed in thenon-active area 141. A plan view (top view) of the structure of FIG. 11Ais shown in FIG. 11B.

Next, as shown in FIG. 11C, source fingers 114′, gate fingers 115′, anddrain fingers 116′ are formed over the III-Nitride layers in the activearea 140 of the device. The source and drain fingers 114′ and 116′,respectively, form ohmic contacts to the 2 DEG channel 133, and the gatefingers 115′ modulate the charge density in the 2 DEG channel 133directly beneath the gate fingers 115′. As shown in FIG. 11D, aninsulator layer 135 is formed over the entire device active area 140,and optionally over the entire non-active area 141 as well. In FIG. 11D,the perimeters of the device active area, as well as those of thesource, gate, and drain fingers, are shown as dashed lines to indicatetheir position beneath the insulator layer 135. Next, vias 143 areetched through the entire thickness of the insulator layer 135 overportions of the source fingers 114′, and vias 144 are etched through theentire thickness of the insulator layer 135 over portions of the drainfingers 116′. Although not shown in FIG. 11D, vias are formed throughthe entire thickness of the insulator layer 135 over the gate fingers115′ as well.

Next, as seen in FIG. 11E, source and drain electrodes 114 and 116,respectively, are formed on insulator layer 135. Source electrode 114 isformed over vias 143 (shown in FIG. 11D) and contacts the source fingers114′ (FIG. 11C) in these vias, and drain electrode 116 is formed overvias 144 (shown in FIG. 11D) and contacts the drain fingers 116′ (FIG.11C) in these vias, thereby completing D-mode transistor 108. Althoughnot shown, a gate electrode is also formed over insulator layer 135which contacts gate fingers 115′ (shown in FIG. 11C).

Hybrid device 107 is then formed by connecting E-mode transistor 109 toD-mode transistor 108 as shown in FIG. 11F. E-mode transistor 109 isplaced directly over the source electrode 114 of D-mode transistor 108,with the drain electrode of E-mode transistor 109 directly contactingsource electrode 114 of D-mode transistor 108. As shown in FIG. 11F, theupper portion of E-mode transistor 109 is directly over the activedevice area 140 of D-mode transistor 108, while the lower portion ofE-mode transistor 109 is directly over the non-active device area 141 ofD-mode transistor 108. Although not shown in FIG. 11F, source electrode111 of E-mode transistor 109 is connected to the gate electrode 115 ofD-mode transistor 108, for example with wirebonds, as was shown in FIG.10A.

Although not shown in FIGS. 11E-11F, it is possible to extend the sourceelectrode 114 over the non-active area 141 and have E-mode transistor109 be entirely over the non-active device area 141 of D-mode transistor108. This can be preferable in that it allows for more effectivedissipation of heat from E-mode transistor 109 during operation, sincethe average temperature in the active device area 140 of D-modetransistor 108 is greater than that in the non-active area 141. If heatgenerated during operation of E-mode transistor 109 is not dissipatedsufficiently, the temperature of E-mode transistor 109 increases, whichcan lead to lower efficiency and/or device failure. However, having atleast a portion of E-mode transistor 109 over the active device area 140reduces the material costs as well as the total footprint of the device.

In order for heat to be effectively dissipated from E-mode transistor109 during operation in structures where the E-mode transistor 109 is atleast partially over the active device area 140 of the D-mode transistor108, the thermal resistance between the E-mode transistor 109 and theD-mode transistor 108 can be made as small as possible. This can beachieved by increasing the cumulative area of all the vias 143 that arebelow source electrode 114, so that the ratio of the total via area tothe total area of source electrode 114 is as large as possible. Forexample, the total via area can be at least 10% of the total area ofsource electrode 114.

As used herein, a “hybrid enhancement-mode electronic device orcomponent”, or simply a “hybrid device or component”, is an electronicdevice or component formed of a depletion-mode transistor and aenhancement-mode transistor, where the depletion-mode transistor iscapable of a higher operating and/or breakdown voltage as compared tothe enhancement-mode transistor, and the hybrid device or component isconfigured to operate similarly to a single enhancement-mode transistorwith a breakdown and/or operating voltage about as high as that of thedepletion-mode transistor. That is, a hybrid enhancement-mode device orcomponent includes at least 3 nodes having the following properties.When the first node (source node) and second node (gate node) are heldat the same voltage, the hybrid enhancement-mode device or component canblock a positive high voltage (i.e., a voltage larger than the maximumvoltage that the enhancement-mode transistor is capable of blocking)applied to the third node (drain node) relative to the source node. Whenthe gate node is held at a sufficiently positive voltage (i.e., greaterthan the threshold voltage of the enhancement-mode transistor) relativeto the source node, current passes from the source node to the drainnode or from the drain node to the source node when a sufficientlypositive voltage is applied to the drain node relative to the sourcenode. When the enhancement-mode transistor is a low-voltage device andthe depletion-mode transistor is a high-voltage device, the hybridcomponent can operate similarly to a single high-voltageenhancement-mode transistor. The depletion-mode transistor can have abreakdown and/or maximum operating voltage that is at least two times,at least three times, at least five times, at least ten times, or atleast twenty times that of the enhancement-mode transistor.

As used herein, a “high-voltage device”, such as a high-voltagetransistor, is an electronic device which is optimized for high-voltageswitching applications. That is, when the transistor is off, it iscapable of blocking high voltages, such as about 300V or higher, about600V or higher, about 1200V or higher, or about 1700V or higher, andwhen the transistor is on, it has a sufficiently low on-resistance(R_(ON)) for the application in which it is used, i.e., it experiencessufficiently low conduction loss when a substantial current passesthrough the device. A high-voltage device can at least be capable ofblocking a voltage equal to the high-voltage supply or the maximumvoltage in the circuit for which it is used. A high-voltage device maybe capable of blocking 300V, 600V, 1200V, 1700V, or other suitableblocking voltage required by the application. In other words, ahigh-voltage device can block any voltage between 0V and at leastV_(max), where V_(max) is the maximum voltage that could be supplied bythe circuit or power supply. In some implementations, a high-voltagedevice can block any voltage between 0V and at least 2*V_(max). As usedherein, a “low-voltage device”, such as a low-voltage transistor, is anelectronic device which is capable of blocking low voltages, such asbetween 0V and V_(low) (where V_(low) is less than V_(max)), but is notcapable of blocking voltages higher than V_(low). In someimplementations, V_(low) is equal to about |V_(th)|, greater than|V_(th)|,about 2*|V_(th)|, about 3*|V_(th)|, or between about |V_(th)|and 3*|V_(th)|, where |V_(th)| is the absolute value of the thresholdvoltage of a high-voltage transistor, such as a high-voltage-depletionmode transistor, contained within the hybrid component in which alow-voltage transistor is used. In other implementations, V_(low) isabout 10V, about 20V, about 30V, about 40V, or between about 5V and 50V,such as between about 10V and 40V. In yet other implementations, V_(low)is less than about 0.5*V_(max), less than about 0.3*V_(max), less thanabout 0.1*V_(max), less than about 0.05*V_(max), or less than about0.02*V_(max).

In typical power switching applications in which high-voltage switchingtransistors are used, the transistor is during the majority of time inone of two states. In the first state, which is commonly referred to asthe “on state”, the voltage at the gate electrode relative to the sourceelectrode is higher than the transistor threshold voltage, andsubstantial current flows through the transistor. In this state, thevoltage difference between the source and drain is typically low,usually no more than a few volts, such as about 0.1-5 volts. In thesecond state, which is commonly referred to as the “off state”, thevoltage at the gate electrode relative to the source electrode is lowerthan the transistor threshold voltage, and no substantial current, apartfrom off-state leakage current, flows through the transistor. In thissecond state, the voltage between the source and drain can rangeanywhere from about 0V to the value of the circuit high voltage supply,which in some cases can be as high as 100V, 300V, 600V, 1200V, 1700V, orhigher, but can be less than the breakdown voltage of the transistor. Insome applications, inductive elements in the circuit cause the voltagebetween the source and drain to be even higher than the circuit highvoltage supply. Additionally, there are short times immediately afterthe gate has been switched on or off during which the transistor is in atransition mode between the two states described above. When thetransistor is in the off state, it is said to be “blocking a voltage”between the source and drain. As used herein, “blocking a voltage”refers to the ability of a transistor, device, or component to preventsignificant current, such as current that is greater than 0.001 timesthe average operating current during regular on-state conduction, fromflowing through the transistor, device, or component when a voltage isapplied across the transistor, device, or component. In other words,while a transistor, device, or component is blocking a voltage that isapplied across it, the total current passing through the transistor,device, or component will not be greater than 0.001 times the averageoperating current during regular on-state conduction.

In some cases, the transistors of half bridges such as 121″-123″ of FIG.7 are not capable of carrying sufficiently large currents for theparticular circuit application. In these cases, half bridges 121″-123″can be modified such the high-side and low-side transistors are eachreplaced by two transistors connected in parallel. A layout for such ahalf bridge configuration is illustrated in FIG. 12. The layout of FIG.12 is optimized to minimize parasitic inductances between parallelconnected transistors.

In the half bridge of FIG. 12, high-side transistors 105′ and 105″ areconnected in parallel, with their respective sources and drainselectrically connected, as are low-side transistors 106′ and 106″. Thesources of transistors 105′ and 105″ are connected to a common sourcelead, and the gates of transistors 105′ and 105″ are connected to acommon gate lead. The sources of transistors 106′ and 106″ are connectedto a common source lead, and the gates of transistors 106′ and 106″ areconnected to a common gate lead. The source and gate leads 88 and 87,respectively, of transistors 105′/105″ are both on a third DBC substrate126. Trenches are etched through the upper metal layer of DBC substrate126 in order to electrically isolate leads 88 and 87 from one another,and from the remaining portions of the upper metal layer of DBCsubstrate 126. As seen in FIG. 12, one of the trenches surrounds sourcelead 88, and the other trench surrounds gate lead 87. DBC substrate 126is mounted directly over DBC substrate 96′, such that the upper metallayer of DBC substrate 96′ passes underneath and is continuous beneathDBC substrate 126. Having the upper metal layer of DBC substrate 96′ becontinuous reduces parasitic inductances between the sources oftransistors 105′ and 105″, and between the drains of transistors 106′and 106″, thereby improving performance during switching.

The circuits described herein are designed such that the transistors canbe switched at high switching rates without destabilizing the circuit orcausing damage to circuit components. For example, when transistors suchas III-N HEMTs, which are typically capable of high switching rates, areused for transistors 105′/105″ and 106′/106″, voltage switching ratesdV/dt of greater than 40 Volts/nanosecond and current switching ratesdI/dt of greater than 5 Amps/nanosecond are possible without causing thevoltage across any of the transistors during switching to exceed2*V_(high), where V_(high) is the circuit high voltage. In some cases,voltage switching rates dV/dt of greater than 90 Volts/nanosecond andcurrent switching rates dI/dt of greater than 10 Amps/nanosecond arepossible without causing the voltage across any of the transistorsduring switching to exceed 2*V_(high) or 1.5*V_(high).

FIGS. 13A and 13B illustrate the current and voltage devicecharacteristics during a switching sequence for switching the high-sidedevice (FIG. 13A) and low-side device (FIG. 13B) of a half-bridge inorder to increase the load (i.e., inductor) current from 0 Amps to 50Amps, where the half bridge power inverter was operated with a 520V highvoltage supply (i.e., a power supply providing a voltage greater than500V). The half-bridge was designed similarly to that of FIG. 12, exceptthat hybrid switching devices such as those of FIGS. 10A-10B or FIG. 11Fwere used in place of transistors 105′/105″ and 106′/106″. The high-sidedevice refers to the device which is connected to the high-voltagesupply, for example transistors 105′/105″ in FIG. 12. The low-sidedevice refers to the device which is connected to DC ground, for exampledevices 106′/106″ in FIG. 12. The switching time for the transistors wasset to 3 nanoseconds, which is less than 5 nanoseconds, andsubstantially less than the 10 nanosecond switching times that would berequired of circuits with higher parasitic inductances. As seen, whenthe high-side device is switched from an on-state in which it conducted50 Amps or less, such as between 40 and 50 Amps, to an off state inwhich the entire high voltage was blocked by the high-side device, thevoltage across the high-side device never exceeds 700V, which is 1.35times the circuit high voltage. When the current switched through thehigh-side device is less than 30 Amps, for example between 20 and 30Amps, the voltage across the high-side device never exceeds 630V, whichis about 1.21 times the circuit high voltage. When the low-side deviceis switched from an on-state in which it conducted 50 Amps or less, forexample between 40 and 50 Amps, to an off state in which the entire highvoltage is blocked by the low-side device, the voltage across thelow-side device also never exceeds 700V, which is 1.35 times the circuithigh voltage. When the current switched is less than 30 Amps, forexample between 20 and 30 Amps, the voltage across the high-side devicenever exceeds 610V, which is about 1.17 times the circuit high voltage.The voltages in excess of the high voltage supply supported across thehigh-side and low-side transistors are lower than those that could beachieved with conventional power converters.

A number of implementations have been described. Nevertheless, it willbe understood that various modifications may be made without departingfrom the spirit and scope of the techniques and devices describedherein. Accordingly, other implementations are within the scope of thefollowing claims.

What is claimed is:
 1. An electronic device, comprising: anenhancement-mode transistor comprising a first source electrode, a firstgate electrode, a first drain electrode, and a first semiconductorlayer, wherein the first source and first gate electrodes are on anopposite side of the first semiconductor layer from the first gateelectrode; and a depletion-mode transistor comprising a second sourceelectrode and a second gate electrode, the second source electrode beingover a second semiconductor layer; wherein the enhancement-modetransistor is mounted directly on top of or over the second sourceelectrode, with the first drain electrode in electrical contact with thesecond source electrode.
 2. The electronic device of claim 1, whereinthe depletion-mode transistor further comprises a second drainelectrode, and the second source and drain electrodes are both on afirst side of the second semiconductor layer.
 3. The electronic deviceof claim 2, wherein the depletion-mode transistor is a lateral device.4. The electronic device of claim 3, wherein the enhancement-modetransistor is a silicon-based transistor.
 5. The electronic device ofclaim 4, wherein the depletion-mode transistor is a III-Nitridetransistor.
 6. The electronic device of claim 1, wherein the firstsource electrode is electrically connected to the second gate electrode.7. The electronic device of claim 1, wherein the depletion-modetransistor comprises an insulator layer on the semiconductor layer, andthe second source electrode is on the insulator layer.
 8. The electronicdevice of claim 7, the depletion-mode transistor comprising a deviceactive area and a non-active area, wherein a device channel is in thesemiconductor layer in the device active area but not in thesemiconductor layer in the non-active area, and the insulator layer isover both the device active area and the non-active area.
 9. Theelectronic device of claim 8, wherein the enhancement-mode transistor ison the insulating layer and is directly over a portion of the deviceactive area and a portion of the non-active area.
 10. The electronicdevice of claim 1, wherein the depletion-mode transistor has a higherbreakdown voltage than the enhancement-mode transistor.
 11. A method offorming an electronic device, the method comprising: providing anenhancement-mode transistor comprising a first source electrode, a firstgate electrode, a first drain electrode, and a first semiconductorlayer, wherein the first source and first gate electrodes are on anopposite side of the first semiconductor layer from the first gateelectrode; providing a depletion-mode transistor comprising a secondsource electrode and a second gate electrode, the second sourceelectrode being over a second semiconductor layer; and mounting theenhancement-mode transistor directly on top of or over the second sourceelectrode, with the first drain electrode in electrical contact with thesecond source electrode.
 12. The method of claim 11, wherein thedepletion-mode transistor is a lateral device.
 13. The method of claim11, further comprising wire bonding the second gate electrode to thefirst source electrode.